1. Field of the Invention
This invention relates to improvements in method and apparatus for accurate automated alignment of semiconductor chips, thin-film networks, or the like, in a manufacturing environment.
2. Relevant Background
There is a need for accurate placement of semiconductor chips and/or thin-film networks (TFNs) in semiconductor component manufacturing. Current pick-and-place machines (used extensively in silicon manufacturing) have typical accuracy of no better than 0.5 mil (12.5 .mu.m), which is generally considered coarse by current integrated circuit standards.
One application in which the need for accurate placement of chips is apparent is in the vertical stacking of chips. In one approach to the fabrication of three-dimensional integrated circuits, completed chips, TFNs, or the like, are stacked on top of each other with vertical interconnections between layers. Precise alignment between different levels in the stack is not easy to achieve or maintain during the stacking process, since each overlying chip obscures the one below it. Relying on the chip edges for alignment is not accurate, since the chip edges are defined by sawing or scribing rather than the more accurate photolithography used for other alignments.
Also, for stacking of multiple layers, there is a need for stabilization of the stack until the alignment is permanently locked in by some process step, such as an epoxy curing step or solder step. Unless alignment of lower levels is somehow maintained during stacking of subsequent levels, an alignment lock-in step is required every time another layer is added to the stack, increasing the time and cost of the assembly.